`timescale 1ns/1ns
module compare_4_tb; 
	reg[3:0] x,y;
	wire[2:0] data_out;
	compare_4 E(.x (x),.y (y),.data_out(out));
	initial begin
		x=1;y=1;#100;
		x=1;y=2;#100;
		x=1;y=0;#100;
	end
endmodule
